1. Field of the Invention
This invention relates to an improvement of an analog-digital converter, and in particular to improving conversion accuracy of a high sampling rate monolithic analog-to-digital converter array for sequentially driving a plurality of analog-to-digital converter circuits in time interleaved manner.
2. Description of the Prior Art
One conventional technique for converting an analog signal to a digital signal at a high speed is a flash conversion technique where comparators formed on one chip are parallel-operated in order to convert an incoming analog signal very rapidly into an n-bit digital signal.
The flash conversion technique is less advantageous since it requires a large number of comparators to be provided on a semiconductor chip, thereby making it necessary for the chip size to be increased. In an attempt to overcome the shortcomings of the flash conversion technique, W. C. Black et al. proposed a high-speed analog-to-digital converter (hereinafter also referred to as an A/D converter) which provides a reduced chip size and less power consumption in an article entitled, "Interleaved Converter Arrays", 1980 IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 13, 1980, pp. 14-15. W. C. Black et al. teach to arrange a plurality of analog-to-digital converters in the array (of columns or of rows and columns) and to activate or enable sequentially these analog-to-digital converters to obtain analog-to-digital converted outputs in a time divisionally multiplexed fashion. Referring to FIGS. 1 and 2, description is made of the architecture and operation of the conventional high-speed analog-to-digital converter. The analog-to-digital converter of FIG. 1 is designed to achieve a conversion rate m times as great as the sampling rate of an individual analog-to-digital converter unit using a plurality of analog-to-digital converter units in the number of m.
As shown in FIG. 1, the A/D converter includes a plurality of n-bit A/D converter units or subconverters 10-1 to 10-m which are arranged in one-dimensional array. The A/D subconverters 10-1 to 10-m are each supplied with an analog input signal V.sub.IN via an input terminal 202. A timing controller 401 provides operating timing or sample/hold timing for each of the analog-digital subconverters. The timing controller 401 comprises a timing controlling unit 201, and a plurality of signal lines 1-1 to 1-m which connect the output terminals 1 through m of the timing control units to the control inputs of the A/D subconverters 10-1 through 10-m. The timing controller unit 201 operates to supply active control signals from its output terminals 1 through m to the control inputs of the A/D subconverters 10-1 through 10-m at predetermined time intervals.
The A/D converter also includes a time multiplexing circuit 204 for selectively receiving output signals from the A/D subconverters 10-1 through 10-m. The time multiplexing circuit 204 functions to sequentially connect the output lines 50-1 through 50-m of the A/D subconverters to its output terminal 203. The output of each of the A/D subconverters 10-1 through 10-m is of an n-bit signal, while the outputs of output lines 50-1 to 50-m and the time multiplexing circuit 204 have an n-bit width. The operation of the analog-to-digital converter of FIG. 1 is now described with reference to FIG. 2 which shows a timing diagram for the analog-to-digital converter. In FIG. 2, the waveforms (a)-(l) are illustrative of operating timings for the A/D subconverters 10-1 to 10-m, respectively, and the output data stream to be applied to the output terminal 203 is illustrated at (m). The timing at which each of the A/D subconverters 10-1 to 10-m samples the incoming analog signal is provided by the timing controller 401. The analog input signals sampled by the A/D subconverters 10-1 to 10-m are converted into n-bit digital data signals which are fed out therefrom with a predetermined time delay. Assuming that the sampling period of the individual A/D subconverters to be Ts, this sampling period Ts corresponds to the period of time of operation during which the timing controller unit 201 supplies one activating signal from all of its output terminals 1 through m. Thus, the activating signals are sequentially applied to the subconverters 10-1 to 10-m from the timing controller unit 201 at the interval of Ts/m.
When the A/D subconverter 10-1 is activated by the enabling signal from the output terminal 1 of the timing controller unit 201, the activated subconverter samples the analog input signal being supplied thereto at the moment S1 and converts it into an N-bit digital signal. At the time S2 upon the lapse of the time of Ts/m after the sampling time S1, the unit 201 feeds a sampling enable signal from the terminal 2 to the control input of the second A/D subconverter 10-2. Upon receipt of the sampling enable signal, the subconverter 10-2 operates to sample the analog input value being applied thereto. In a similar manner, the timing controller unit 201 successively generates the sampling enable signals at the time interval Ts/m and supplies them to the control inputs of the A/D converters 10-3 to 10-m in sequence. In response to the sequential application of the sampling enable signal, the A/D subconverters 10-3 to 10-m function one after another to sample the analog input value V.sub.IN being supplied thereto at the time of sampling. As the final A/D subconverter 10-m finishes the sampling, the timing controller unit 201 provides the sampling enable signal at the output terminal 1. Accordingly, during the single sampling cycle of a single A/D subconverter, m A/D subconverters sequentially perform the sampling of the applied analog signal.
On the other hand, each of the A/D subconverters 10-1 to 10-m provides the N-bit digital value with the delay of Td with respect to the sampling time. This means that the input terminals 50-1 to 50-m of the time multiplexing circuit 204 each receive the digital data signal Di from the respective A/D subconverters which corresponds to the sampled analog input upon the lapse of the time Td after the analog input has been sampled at the time Si. Phrased differently, the A/D subconverters generate digital output signals sequentially upon the passage of the delay time Td after the sampling time at the interval of Ts/m. In the sampling cycle of operation, at the time M1 upon the completion of the delay time Ts after the time S1 when the A/D subconverter 10-1 has sampled the analog input, the time multiplexing circuit 204 is activated to select the digital signal supplied to the input terminal 50-1 and transfers it to the output terminal 203. In this manner, the timing multiplexing circuit 204 operates, under the control of the timing controller 401, in synchronization with the generation of the sampling enable signals from the timing controller unit 201, thereby successively linking the input terminals 50-1 through 50-m to the output terminal 203. The time multiplexing circuit 204 provides m digital data signals to its output terminal 203 in a time duration of Ts.
With the A/D converter of the time interleaved array design, although the individual A/D subconverters have a relatively long sampling period, the use of the time multiplexing circuit 204 for sequential selection of the digital outputs from the A/D subconverters, in effect, reduces substantially the sampling period to 1/m of Ts. This in turn is effective to provide digital signals at the output terminal 203 which are sampled and converted at a high speed of a sampling rate 1/m times greater than that of the individual A/D subconverters.
The fact that all of the A/D subconverters in the conventional time interleaved A/D converter array are monolithically integrated on a single chip poses some serious problems as will be explained below.
Referring to FIG. 3, there are illustrated plotted curves representing the conversion characteristics of the individual A/D subconverters 10-1 to 10-m as indicated by the curves 30-1 to 30-m, and of the whole A/D converter as indicated by the bold curve 307. It is assumed that a linearly increasing ramp signal is applied as an analog input signal to be A/D converted.
From the ideal point of view, the conversion characteristics of the A/D subconverters 10-1 to 10-m should coincide with one another. However, as a practical matter, they never coincide because the component devices such as transistors have different performance characteristics for the various reasons traceable into the manufacturing process, and because of the thermal gradient in the semiconductor substrate on which the component devices are formed. As far as the operation characteristics of the component devices and the thermal distribution on a chip are concerned, the more remote the subconverters are disposed, the greater the difference of the devices characteristics and the thermal distribution. All these give rise to a corresponding difference in the conversion characteristics of the A/D subconverters. Even in a design of the A/D converter where the A/D subconverters are arranged discretely on, for example, a printed circuit board instead of being monolithically formed on a semiconductor chip, the subconverters are placed under widely differing heat conditions due to the thermal gradient. Thus, the subconverters at remote locations on the print circuit board exhibit different conversion characteristics.
When the A/D subconverters 10-1 to 10-m perform the sampling operation of an incoming analog signal in a sequence and manner as stated previously, the outputs in digital form obtained at the converter output terminal 203 are shown moving from one conversion characteristic curve to another starting on the characteristic curve 30-1 at the time S1. Then, the overall conversion characteristic of all the subconverters combined is obtained as indicated by the bold curve 307.
As the sampling operation goes on, the A/D subconverter 10-m performs a sampling operation, followed by a sampling operation of the A/D subconverter 10-1. Thus, as shown by a encircled portion 308 of a large difference in the conversion characteristics in FIG. 3, the converted outputs appearing at the output terminal 203 have a larger difference between the time S1 and the time S2. More specifically, in the conventional time interleaved A/D converter, the A/D subconverters included therein are sequentially activated in a roll-over manner. Therefore, the A/D subconverters with a large physical separation are successively activated to provide an output data, and it follows that much different levels of the A/D converted signals are generated in that region. In other words, the conventional time interleaved A/D converter has a drawback that the differential linearity, which is one of the most important characteristics in the A/D converter performance, tends to be degraded and poor.
Although the aforementioned article by W. C. Black et al does describe the architecture and operation of the time interleaved A/D converter array, it makes no mention of the problems of non-uniform characteristics and the degraded differential linearity in the performance of the converter array.